About the roleCritical role in connectivity technology through innovative design, development, and testing; ideal for candidates experienced in charge‑pump PLL, FracN‑PLL, Digital‑PLL, high‑speed clock distribution, and high‑speed digital design/analysis.Base salary range is $120,000 to $140,000 a year. Eligible for bonus, equity, and full benefits.Responsibilities- Design/optimize analog and mixed‑signal circuits; collaborate across teams; analyze test data and improve quality/yield; support product lifecycle; document specs.Qualifications- Master’s in EE/CE or related; 1+ year industry experience (internship acceptable); familiarity with PLLs and high‑speed distribution; EDA tools (Cadence/Synopsys).