About the roleLead front‑end ASIC design including architecture, implementation, and verification of complex logic blocks; collaborate across teams to ensure successful tape‑outs and chip bring‑up.Base salary range is $140,000 to $170,000 a year. Eligible for bonus, equity, and full benefits.Responsibilities- Write microarchitecture/design specs; architect/implement/debug logic.- Integrate complex IPs; support Lint, CDC, Synthesis, ECO.- Develop testbenches; run RTL and Gate‑Level verification.- Work with DV/DFT/PD; bring‑up, validate, and debug features.Qualifications- BS/MS in EE/CE; 5–10 years digital ASIC design; Verilog/SystemVerilog; UVM familiarity; scripting (Python/Tcl/Perl/Shell).