About the roleLead a team delivering complex ASIC designs from spec to tape‑out. Cover microarchitecture, RTL implementation, and verification for complex logic blocks; collaborate with PD/DFT/STA/integration to ensure successful tape‑outs and chip bring‑up.Base salary range is $200,000 to $230,000 a year. Eligible for bonus, equity, and full benefits.Responsibilities- Lead team to deliver chips; mentor juniors; develop specs; design/debug logic; integrate/validate IPs; support front‑end integration; create tests/testbenches; collaborate cross‑functionally; bring up/validate silicon.Qualifications- MS EE/CS with 10+ years; Verilog/SystemVerilog; STA/timing closure; DFT/PD familiarity; high‑speed SerDes experience.